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Vesuvius

Vesuvius is a highly integrated System-on-a-Chip (SOC) Device Under Test (DUT) power supply solution incorporating 8 independent DUT Power Supply (DPS) units.

The interface, the control, and the I/O are digital; all analog circuitry is inside the chip. For most tester applications, no additional analog hardware needs to be developed or used on a per channel basis.

All configuration setup and the writing to and reading back of the internal registers are controlled through the 3-bit serial data CPU port. The CPU port is typically used to setup the operating conditions of each channel prior to executing a test, or to change modes during a test.

An internal register chart (Memory Map), listed later in the data sheet, lists all programmable control signals and their addresses. Real time control is accomplished via the central EN and DATA_# pins. Real time observation is accomplished via the central monitor.

venus designs

Features

    • Per Channel DPS
      • FV, FI, MV, MI, HiZ Capability
      • 16V Measure Voltage Input Compliance Range
      • 2 Force Voltage Ranges (8V, 16V)
      • 3 Measure Voltage Ranges (4V, 8V, 16V)
      • 6 Current Ranges: (512mA, 25.6mA, 2.56mA, 256μA,
        25.6μA, 2.56μA)
      • Programmable Voltage and Current Clamps
    • Power Management
      • Independent Output Buffer Power Supply (VCCO)
      • Ability to Exceed VCCO in Lower Current Ranges (Patent
        Pending)
    • Flexible Ganging Capability
      • No Restrictions on Maximum # DPS Units
    • 3-Bit Serial CPU Port
    • Protection
      • On-Chip Junction Temperature Monitor
      • Over-Temperature Shut Down per Chip
      • Kelvin Connection Sensing/Alarm per Channel
      • Over-Current Sensing/Alarm per Channel
    • Monitor
      • One General Purpose Central Monitor per Chip
        • Scaling and Shifting Capability
        • HiZ Capability
      • One Dedicated Measure Current Monitor per Chip
        • Scaling and Shifting Capability
        • HiZ Capability
      • Eight Independent V/I Monitors Per Chip
        • Maximum Measurement Throughput
    • Global External Force/Sense Connectable to any Channel
    • On-Chip DAC to Generate DC Levels
      • 2 Independent FV Levels/Channel
      • Central Resource Mode w/16 Selectable Levels
      • Independent Source and Sink Clamp Levels/Channel
      • 16 bits/Level
      • On-Chip Offset and Gain Correction per Level
    • Package/Power Dissipation
      • Pb-Free (RoHS Compliant)
      • 128 Lead, 14mmx20mm, LQFP w/Exp Heat Slug
      • Pdq 115mW/Channel; Pdq 920mW/Chip
    • Applications
      • Automated Test Equipment
      • Logic/ASIC Verifiers
      • Instrumentation
vesuvius diagram

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VESUVIUS
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Europa ISL55180
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