MYSTERY
8 Channel, Pin Electronics/DAC/
PPMU/Deskew
Elevate’s data center test solutions feature standard or custom designed skus to reduce cost of test for data center applications like artificial intelligence, machine learning, content streaming, remote collaboration and cloud based services.
VESUVIUS
DPS with 8 independent DUT Power Supply units
Data Center Solutions
Semiconductor test ICs for the hyperscale modern data center. ElevATEs solutions feature; High-Density Low-Voltage Pin Electronics, Wide-Voltage DACs and High-Efficiency DPS Solutions.
Data Center CPUs and AI
Microprocessor test is becoming more difficult and more time consuming as these devices are designed to take on more complex tasks, such as accelerating artificial intelligence computing. This is not just limited to microprocessors, either. Graphics processing units are grabbing market share in supercomputing and MPUs and Microcontrollers are now more complex then ever before.
Memory
There are two main categories of memory used in the modern datacenter, DRAM and Flash. DRAM is used in computing devices and graphics adaptors, while Flash is used as a storage media in solid-state drive devices. The advancement of memory technology has been a constant together with keeping memory costs constant or lower. This presents a significant challenge for cost effective memory testing,
Power and Measurement
Parametric measurement units (PMUs) and device power supply (DPS) products offer a flexible range of voltage and current source/measurement capability to meet the needs for datacenter semiconductor test applications. ElevATE DPS products support larger voltage ranges and more channels allowing ATE manufacturers to test more ICs at the same time and at a lower cost.
ElevATE Product Selection Guide
Click below to download our latest product selection guide.
Semiconducter Test ICs for Datacenter Applications
Elevate is the market leader in Semiconductor Test. Our products enable customers to develop next generation high density instruments with increased parallelism for reduced cost of test and improved system reliability.