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Using FPGA for Format and Timing Generation for Semiconductor ATE

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ATE digital systems traditionally consist of sequencers, formatters, timing generators and pin electronics. The decision about which components to use for each section of the design is primarily driven by performance specifications and cost desired. These components range from discrete, fully custom ASIC, Field Programmable Gate Array or commercially available parts.

Field Programmable Gate Arrays (FPGA) provide flexibility and have been used for the sequencer and timing/formatting for low to medium performance ATE digital subsystems.

Implementing the sequencer with an FPGA provides flexibility to customize the digital subsystem for logic, memory or mixed signal test. The FPGA clocking required is typically well within the specifications of the target FPGA. The sequencer and pattern execution stages are typically what make each system unique compared to the competitors offering.

The format and timing functionality are typically similar amongst different ATE platforms. The differences are in the cycle to cycle edge placement resolution and accuracy as well as the fine skew control used for channel deskew calibration. The fine deskew control is often available in the pin electronics ICs.

FPGAs have been successfully used for the timing and format function, but the FPGA quickly becomes the limiting factor as the system performance requirements increase to above 50-100Mhz pattern rates and as the system edge placement accuracy is pushed below 1ns. While the SERDES engines in the FPGA I/O structures can provide <100ps resolution, implementing this reliability for edge to edge timing placement increases the design time and pushes the designer to choose larger and more expensive FPGA.

The most common usage of the SERDES blocks are for various communications protocols such as PCIe and the FPGA design tools provide excellent tools for designing and characterizing these functions. Designers often run into roadblocks when designing the timing section using these SERDES blocks and there are limited tools available from FPGA vendors to resolve issues. Designers often spend 10X the budgeted engineering hours implementing and characterizing these timing circuits. Typical issues include: inconsistent linearity from channel to channel, higher than acceptable jitter, and difficulty routing the design from run to run.

As designers attempt to increase the channel count they are required to migrate to larger and more expensive FPGAs. In the past, designers have been able to capitalize on faster and larger FPGAs at lower costs. In recent times, however, the focus of FPGA companies has been to increase compute capabilities to address the data center and artificial intelligence markets. This addition of more compute elements has increased the costs with minimal or negative benefits to the ATE designer. In addition, the costs of older devices that serve the ATE market have started going up dramatically especially for larger devices. This has pushed the cost for higher channel ATE using larger FPGAs up to $50/channel just for the FPGA.

To achieve higher performance ATE with pattern rates of 200+ MHz, ATE designers need to use custom or commercially available format and timing generator ICs. They are then able to use a reasonable cost FPGA for the sequencer portion of the design.

A commercially available timing generator would provide smaller ATE companies to migrate up the performance ladder in digital ATE instrumentation. These chips are designed to be interfaced to high performance pin drivers without requiring an over constrained FPGA I/O.

By purchasing timing chips with high end performance this would reduce the design, characterization and test times as well as reducing the cost per channel while offering higher performance digital ATE specifications. The timing accuracy is specified by the vendor and does not require extensive characterization and production testing of these parameters at system test.

Commercial timing chips will ultimately save an ATE company development cost and time to market as well as overall cost of the system, while providing a path to higher end performance.

MIPI5G 200

MIPI Specifications and Testing

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The mobile industry processor interface (MIPI®) standard defines industry specifications for the design of mobile devices such as smartphones, tablets, laptops and hybrid devices. MIPI interfaces play a strategic role in 5G mobile devices, connected car and Internet of Things (IoT) solutions. The MIPI standard defines three unique physical (PHY) layer specifications: MIPI D-PHY®, M-PHY® and C-PHY®. MIPI D-PHY and C-PHY physical layers support camera and display applications, while the high-performance camera, memory and chip-to-chip applications are supported on top of the M-PHY layer.

MIPI is managed by MIPI Alliance which is a collaboration of mobile industry leaders which include Intel, Nokia, Samsung, Motorola, TI, ST etc.  The objective of MIPI Alliance is to promote open standards for interfaces to mobile application processors. This will help in having new services to mobile users at faster rate.

In the mobile market, MIPI Alliance specifications are targeted to mobile devices that operate on mobile networks. Typical devices are smartphones, tablets, laptops and hybrid devices. MIPI Alliance provides specifications that serve manufacturers’ various needs for physical layer, multimedia, chip-to-chip or interprocessor communications (IPC), control/data, debug/trace, and software integration applications.

All of the specifications are designed to address three characteristics essential to successful mobile designs:  1) low power to preserve battery life; 2) high-bandwidth to enable feature-rich, data-intensive applications, and 3) low electromagnetic interference (EMI) to minimize interference between radios and other subsystems in a device.

Smartphones

The smartphone industry is the largest single market for MIPI specifications. All major chip vendors use MIPI Alliance specifications and all smartphones on the market include at least one MIPI specification. MIPI specifications are used in hundreds of millions of smartphones.

MIPI Alliance specifications cover the full range of interface needs in a device. The specifications can be applied to integrate the modem, application processor, camera, display, audio, storage, antennas, tuner, power amplifier, filter, switch, battery, sensors, and other components.

Component vendors and device manufacturers use MIPI Alliance specifications because the technologies simplify designs, reduce design costs and shorten time-to-market for efficient, high-performing products. And fundamentally, each specification is optimized to ensure three performance characteristics needed in a mobile device: low power to preserve battery life, high-bandwidth to enable feature-rich applications, and low electromagnetic interference (EMI) to optimize performance of radios and subsystems.

Tablets, laptops and hybrid devices

Devices that converge mobile and computing capabilities are important markets for MIPI Alliance specifications. MIPI specifications helped establish and advance the tablet market and many organizations in the PC industry use MIPI specifications in mobile-connected laptops, tablet/laptop hybrids and other devices. Typical use cases for MIPI specifications in these devices include connecting and managing power consumption for high-definition displays and minimizing the number of wires deployed through hinges to connect cameras or displays.

 Specifications

MIPI specifications address only the interface technology, such as signaling characteristics and protocols; they do not standardize entire application processors or peripherals. Products which utilize MIPI specs will retain many differentiating features. By enabling products which share common MIPI interfaces, system integration is likely to be less burdensome than in the past.[8]

MIPI is agnostic to air interface or wireless telecommunication standards. Because MIPI specifications address only the interface requirements of application processor and peripherals, MIPI compliant products are applicable to all network technologies, including GSM, CDMA2000, WCDMA, PHS, TD-SCDMA, and others.

Some of the specifications by MIPI include:

  • Camera Serial InterfaceDisplay Serial Interface
  • Display pixel interface
  • System Power Management Interface (SPMI)
  • SoundWire, introduced in 2014[12]

MIPI CSI Interface

CSI stands for Camera Serial Interface. It specifies high speed serial interface between a host processor and camera module. Figure-2 depicts MIPI CSI-2 Interface.

Following are the features of MIPI CSI-2 Interface.

  • It is high performance serial interface between image sensor and application processor.
  • It uses D-PHY physical layer with upto 4 data lines which provides data throughput of about 4Gbps.
  • Separate I2C compliant interface used for camera control functions as shown.
  • MIPI CSI interface offers following benefits.
  • Scalability • Lower power • improved reliability • lower system cost

MIPI DSI Interface

 DSI stands for Display Serial Interface. It is High speed and high performance serial interface. The DSI interface offers efficient, low power and low pin count connectivity between application processor and display module (or display bridge IC). It uses MIPI D-PHY as physical layer. Following are the features of MIPI D-PHY.

  • It uses 4 data lines with 1 common differential line
  • Throughput upto 1Gbps can be achieved.
  • Both pixel and data commands are serialized into single physical stream between processor and display IC. The status is conveyed from display IC to application processor.

MIPI Testing

MIPI DESIGN AND SIMULATION

You need to design mobile devices that address the evolving data storage, data transfer, display, camera, memory, power, and other requirements defined by MIPI specifications. Customers demand higher performance, real time streaming of multimedia content and feature-rich applications.

MIPI TRANSMITTER TEST

You need to test the performance of your MIPI transmitter device to ensure it is not the root cause of signal impurities at the receiving end of the transmission line. MIPI D-PHY, M-PHY and C-PHY all have unique transmitter test challenges. With hundreds of tests to be performed, you can save significant test time by using automated compliance test software.

MIPI RECEIVER TEST

You need to test your MIPI receiver device to ensure it can properly detect the digital signal content of an input signal. It is important to test it against a worst-case stress condition to account for signal degradation in the transmission channel. You need an accurate high-speed signal stimulus, as well as bit error detection capabilities, to test the performance of your MIPI receiver. Automated compliance test software enables you to quickly test all key parameters of your designs.

MIPI PROTOCOL TEST

Protocol validation occurs predominately at the interface layer. There are many different protocols supported on the PHY layer of the MIPI specifications, including CSI-2, DSI-1, DigRF, CSI-3, UFS, UniPro, SSIC, and MPCIe. Each protocol has its own unique requirements and tests. For both MIPI D-PHY and M-PHY protocols, there is a stack between the physical and link layer, as well as between the transport and high-level application layer. To truly identify where an error exists, it is ideal to be able to “see into” that stack.

How MIPI Interfaces Enable 5G Smartphones

The first wave (phase 1) of high-end 5G smartphones is expected to be an enhancement of the high-end 4G devices currently on the market. Major enhancements will include the addition of the new 5G NR RF subsystem, and the evolution of other subsystems to enable better user experiences and richer multimedia capabilities. For example, these 5G smartphones may have three to four high-resolution rear cameras with high-frame-rate/slow-motion video capture capability, an enhanced microphone array, multi-channel audio and stereo speakers.

The 5G modem and application processor use MIPI specifications such as CSI-2 for cameras and DSI-2 for the display, as well as either the low-power, high-bandwidth, pin-efficient MIPI D-PHY or C-PHY physical layers. MIPI RFFE for RF front-end devices control, and MIPI UniPro with M-PHY for high-performance flash storage are all becoming ubiquitous in 5G designs. MIPI I3C, SoundWire, SLIMbus and upcoming VGI specifications are expected to be adopted in many upcoming 5G smartphone platforms as well.

MIPI CSI-2

MIPI CSI-2 is the most widely used camera interface in mobile and other markets. It has achieved widespread adoption for its ease of use and ability to support a broad range of high-performance applications, including 1080p, 4K, 8K and beyond video, and high-resolution photography.

Designers should feel comfortable using MIPI CSI-2 for any single- or multi-camera implementation in mobile devices. The interface can also be used to interconnect cameras in head-mounted virtual reality devices; automotive smart-car applications for infotainment, safety, or gesture-based controls; imaging applications for client content creation and consumption products; camera drones; IoT appliances; wearables; and 3D facial recognition security or surveillance systems.

The latest release, MIPI CSI-2 v3.0, delivers enhancements to the specification designed to enable greater capabilities for machine awareness across multiple application spaces, such as mobile, client, automotive, industrial IoT and medical. RAW-24, for representing individual image pixels with 24-bit precision, is intended to enable machines to make decisions from superior quality images; an autonomous vehicle, for example, could decipher whether darkness on an image is a harmless shadow or a pothole in the roadway to be avoided. Smart Region of Interest (SROI)—for analyzing images, inferencing algorithms and making better deductions—could enable machines on a factory floor, for example, to more quickly identify potential defects on a conveyor belt, or medical devices to more surely recognize anomalies such as tumors. And Unified Serial Link (USL)—for encapsulating connections between an image sensor module and application processor—is crucial for reducing the number of wires needed in IoT, automotive and client products for productivity and content creation, such as all-in-one and notebook platforms.

MIPI CSI-2 can be implemented on either of two physical layers from MIPI Alliance: MIPI C-PHY v2.0 or MIPI D-PHY v2.5. It is backward compatible with all previous MIPI CSI-2 specifications. Performance is lane-scalable, delivering, for example, up to 41.1 Gbps using a three-lane (nine-wire) MIPI C-PHY v2.0 interface, or 18 Gbps using four-lane (ten-wire) MIPI D-PHY v2.5 interface under MIPI CSI-2 v2.1.

Testing of MIPI-Specification-Based Devices

The latest trend for semiconductor device manufacturers is to add several high-speed MIPI® specification-based ports to a single device. This enables feature-rich implementations of imaging- and display-intensive applications, although it also poses significant challenges for production test engineers who are tasked with creating high-fault coverage testing solutions on automated test equipment (ATE). Such fault coverage often entails creating a parallel, at-speed, system-oriented functional test while simultaneously grappling with the limitations of legacy ATE and the complexity of the MIPI protocols being tested.

There are three high speed PHY-layer standards defined by MIPI, and they are used for different applications:

  • D-PHY is a variable speed unidirectional clock synchronous streaming interface, with low speed in-band reverse channel and supports interfaces for camera (CSI), and display (DSI).
  • M-PHY is performance driven, bidirectional packet/network oriented interface supporting interfaces like camera (CSI), storage (UFS), DigRF, and the UniPro, LLI, SSIC, M-PCIe which are used for inter-processor communications
  • C-PHY is a variable speed unidirectional, embedded clock streaming interface, with low speed in-band reverse channel and supports interfaces for camera (CSI), and display (DSI).

Each interface provides a wide range of parameters including clocking method, channel compensation, number of pins, maximum amplitude, data rate and format, bandwidth per port, data encoding, and clock recovery. The D-PHY, M-PHY, and C-PHY MIPI interfaces are not controlled by a compliance program because they are not accessible to users. However, validation of specification conformance is important to semiconductor vendors and system integrators to ensure interoperability between components.

The MIPI specifications and Conformance Test Suite (CTS) requirements for components are quite complex and testing them is challenging. Connectivity to the Device Under Test (DUT) while making sure signal integrity is maintained, creating the worst-case stimulus for the DUT while not overstressing it, or getting test result information from the DUT are examples of such challenges.

BER test solutions offer the flexibility to test all types of MIPI receivers accurately by providing accurate high speed signal stimulus and bit error detection capabilities. More complex C-PHY and D-PHY signal stimulation can be addressed with high performance arbitrary waveform generators. Automated test software helps to reduce test development and execution time while ensuring repeatability and accuracy.

Elevate competitive advantage in ATE

Elevate is a leading supplier of innovative, low power, high density components for the design of next generation Automated Test Equipment (ATE). With a proven track record of consistently delivering the highest density, lowest power solutions available, systems designed around Elevate products have a competitive advantage in the ATE market space and are able to adapt successfully to emerging trends and challenges while providing ever increasing end user value.

Elevate offers a wide variety of solutions for the ATE market with variable levels of integration so that we can serve the unique requirements of multiple end user segments such as System on a Chip (SOC) Test, Memory Test, Test During Burn-in (TDBI), In-Circuit Test (ICT) and beyond.

Elevate’s mission is to serve our semiconductor and system test customers by providing world class test integrated circuits (ICs) that address the industry’s most complex ATE challenges.  We strive to exceed our customer’s expectations, now and well into the future, through designing the lowest power/highest density solutions, with the goal of providing the lowest possible cost of test. 

Chip Mask

Elevate Intro

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ELEVATE: WORLD LEADER IN INTEGRATED TEST TECHNOLOGY

THE BASICS OF SEMICONDUCTOR TEST:
Technology aficionados know Moore’s Law which states the number of transistors in a dense integrated circuit doubles every two years. Few think about how those chips are designed, produced, and tested. As silicon content in electronics increase, functionality grows exponentially, requiring size, power, and cost to decrease. The need to test the chips for fabrication defects is essential to provide working components and ensure long life performance. The tests undertaken in production must be suitably comprehensive and at the lowest cost possible. Someone has to build the chips that test ALL these ICs – that company is ElevATE Semiconductor.

At ElevATE, we design and build integrated circuits which test all functions of a semiconductor from the key parametrics: power, speed, voltage, plus the overall system in which the chip is designed to operate. We can identify defects in processing and performance or variation across parameters over time. Our solutions provide all the data I/O, measure the parametrics, supply power, and the power response to the device under test (DUT). Our circuits are accurate enough to characterize the latest high-speed server processors, memory modules, and artificial intelligence (AI) FPGAs used in data center applications.

OUR TEAM:
Ask any engineer and you will be told test engineers are a special breed. Our founders, and many of our team, have been in the semiconductor test space since the early 90’s. A spinout of Intersil in 2012, ElevATE’s heritage goes back to early 2000 as PlanetATE where many of our solutions were first architected. Our customers include the largest semiconductor test companies, startup test firms, test houses, and semiconductor manufacturers. They have procured products which were designed-in over 10 years ago and continue to ship on production boards today. We anticipate our new designs to be available at least that long going forward.

OUR APPROACH:
Our customer’s evolving challenges dictate our next generation of products. Semiconductor test continues its march toward lower test times, with more devices under test simultaneously with the goal of minimizing the costs of testing. We see more demand for the lowest power possible at even higher speeds and higher channel counts, which challenges our engineers to push the limits of process and design.

We focus on test and know importance of quality is for our design, manufacturing, and support processes. ElevATE is ISO9001 certified and a continuous improvement organization. Our products go through rigorous qualification thorough testing and characterization before finding their homes on customer boards – in fact, each chip can go through over 3,000 analog tests before being made ready for shipment.

We offer numerous ways to customize our products to meet the wide variety of our customer’s technical needs. If you have state of the art technology, you need the best test circuits in the world to test it – engage us and see why our experience, portfolio of world class products, and our team are the best in the industry!

SE-DPIN: Scalable (16 .. 256+) I/O card Technology for PXIe and Custom ATE instruments

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Salland Engineering delivers over 28 years of services to develop and build custom ATE instruments for the semiconductor industry. CEO, Paul van Ulsen said; “Building high density instruments is always about finding the right balance between performance, density/throughput within the right available power & cooling at the right cost per channel.“

To address these challenges, Salland decided to design the Instrument IP themselves. This enables customers to benefit from proven & available building blocks to achieve high performance and very high density at the right cost.

Salland’s ‘’off-the-shelf’’ custom OEM instrument solutions allow customers to build  ATE instruments at a fraction of the cost and at minimal risk. In this respect Salland follows a similar approach as Elevate, building standard solutions for custom applications.

Salland’s latest proof of concept is a scalable 200MHz DPin IO technology based on ElevATE’s Mystery Octal SOC ASIC.  This is a 64ch PXIe card with 8 Mystery ICs onboard featuring:

  • 64 (/32)-channel, 200MHz/up to 500Meps Digital I/O card in PXIe format
  • Based on ElevATE Mystery ASIC and a FPGA based timing generator
  • Scalable architecture in blocks of 16 channels up to 256+
  • Technology can be used in all kind of form-factors; modules, ATE, PXIe, etc.

With the Mt. Mystery ASIC, Salland was able to dramatically increase channel count and speed in an air-cooled solution designed to fit into the strict power/space requirements for a PXIe card. 

Air Cooled

SE-DPIN: PXI I/O card Specifications

Form-factor Single slot, 3U PXI
# Channels 64 (or 32) independent I/O
Large Vector Memory 256M vectors
Scan Memory Up to 4G vectors (optional)
Error Memory 1k
Max vector rate 200MHz (39ps Res),  upto 500Meps
Max offset (DGS – GND) ±300mV
High Voltage Mode
Frequency range 100Hz…50MHz
Voltage range -2.0V to +6.0V
High Speed Mode High Speed mode Single ended/Differential LVDS
Frequency range 100Hz…200MHz
Voltage range 0.0V to +4.0V
block to IO card
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ElevATE DPS – Powering the Next Generation of Test

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Device Power Supplies (DPS) semiconductors provide flexible voltage and current force measurement capabilities to meet a wide range of test application needs. Our DPS portfolio of products contain integrated System-on-a-Chip (SOC) solutions incorporating up to 8 independent channels.  The interface, control, and I/O are digital with all analog circuitry integrated into the chip.

ElevATE DPS – Market Leading Features

  • Lowest headroom in the industry. Up to 5x more power efficient.
  • Space Efficient. Best in class density with 2 to 4x improvement.
  • Class leading forced voltage range. (60V Operation Window)  
  • Patented “Glitch Free” voltage range changing.
  • Integrated voltage and current clamps enable DUT protection.
  • Gangable DPS with proven operation beyond 100A.
  • Extreme fast load transient response times
  • High Precision PMU features

ElevATE DPS products meet the power and area density requirements for today’s and tommorrow’s ATE test equipment.  By maximizing the power efficiency of the DPS while reducing footprint, ATE equipment manufacturers can now test more ICs by adding more channels into their test solutions.

ElevATE DPS – Featured Products

Vesuvius – A highly integrated Octal SOC Device Under Test (DUT) power supply solution.  Vesuvius features ultra-low power in a class leading reduced footprint. Learn more about Vesuvius.  https://elevatesemi.com/vesuvius/

Whitney – Dual channel 1A capable DPS with a class leading 60V operating window inside a -60V to +60V range. Learn more about Whitney. https://elevatesemi.com/2020products/

High Efficiency DPS – Quad Channel DPS with glitch-free architecture. Imax = 1A Gangable. Learn more about our High Efficiency DPS. https://elevatesemi.com/2020products/

For more information on ElevATEs full range of DPS products, please visit: https://elevatesemi.com/products-dps/

About ElevATE Semiconductor

Founded in 2012, ElevATE Semiconductor is an industry in the design and manufacturing of automated test equipment (ATE) semiconductors for the automotive, memory, 5G, industrial, LCD, datacenter markets.  Learn more at www.ElevATEsemi.com.

Mystery Pose Chips

Mt. Mystery, Achieving the Pin Electronics Trifecta

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As technology evolves, and demand increases for next generation chips in artificial intelligence, deep learning, machine learning, automotive, IOT, healthcare and other areas, technology to provide faster, higher density and lower power ATE (Automatic Test Equipment) semiconductors is required.

At ElevATE, the goal is to provide our customers with pin electronic (PE) solutions innovating with respect to speed, power,and density.  The company’s new pin electronics chip, Mt. Mystery accomplishes this design trifecta:  increasing speed by 50%, reducing power by 67%, and total size by 75%.  Achieving it through 20+ years of ATE expertise, circuit architecture advancement, and the use of modern sub-micron technology. 

Density.  In design, Mt. Mystery connotes a compact and efficient use of space.  In technology it also delivers the fine balance between speed and  power.  Whether the latest smartphone, data center blade, or ATE test system the triple challenge of speed, power, and density remains a constant. 

The advantage this trifecta brings to the ATE system designer is flexibility across all three axes. 50% speed increase permits the test of the most modern processor, SOC, FPGA, and memory technologies.  67% reduced power permits tripling the number of pins/devices under test without increasing the power budget.  75% reduction in size permits the quadrupling the number pins under test without expanding the overall PCB size versus a current architecture.  Mt. Mystery achieves this trifecta creating the space for the ATE manufacturer to innovate without the hurdles of prior performance constraints.

The technology trifecta delivered by Mt Mystery creates an added benefit.  It permits ElevATE to drive a lower solution cost.  Combined with ElevATEs ISO certification for design and quality this yields a tangible total cost of ownership advantage to our customers.

Mt. Mystery is now available and is a SOC Octal 500Mz integrate pin electronics solution that incorporates every analog function, along with digital support circuitry required to create 8 independent pin channels for automated test equipment.

For information on Mt. Mystery and other ElevATEs PE products, please visit: https://elevatesemi.com/products-pin-electronics/

About ElevATE Semiconductor

Founded in 2012, ElevATE Semiconductor is the worldwide leader in the design and manufacturing of automated test equipment (ATE) semiconductors for the automotive, memory, LCD, industry and IOT markets.  Learn more at www.elevatesemi.com.

5G Technology

5G Test: Issues and Implications

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The fifth-generation of cellular technology, known as 5G, promises to enable a sea change in telecommunications, automation, and computing. Some analysts and futurists have suggested it has the potential to revolutionize society in ways even greater than the internet itself. However, the performance requirements of 5G creates a series of unique challenges for IC/SOC test, PCB assembly test, finished device test, and network equipment conformance test.


5G is the common name for the IMT-2020 performance requirement, defined by the International Telecommunication Union (ITU-R). Technologies that meet the IMT-2020 requirements may market their technologies as 5G, in the same way that technologies meeting the 4G requirements – including Long Term Evolution (LTE) governed by the 3rd Generation Partnership Project (3GPP) family of standards, and WiMAX governed by the Institute of Electrical and Electronics Engineers (IEEE) 802.16 family of standards – were commonly called 4G. 3GPP’s technology for 5G wireless equipment is known as New Radio or “NR”.
Like previous cellular generations that focused on improvement of connectivity for portable computing devices, 5G improves user-experienced data rates by orders of magnitude and reduces latency to nearly real time levels. Additionally, 5G adds support for timing-critical applications like accurate positioning (without need for GPS satellites) for intelligent/autonomous vehicles and virtual or augmented reality, and expands support for Internet of Things (IoT) applications and robotic systems. 5G radios will make use of beamforming and multiple-input, multiple-output (Massive MIMO) antennas that leverage spatial multiplexing and multipath to improve channel performance and spectral efficiency. To reach the performance levels required by 5G, designers will push computing, memory, digital and analog/RF circuitry, and semiconductors to their limits.
Additionally, the complexity of conformance testing required is growing exponentially with each generation of cellular technology; 3GPP Release 14 (which contained some pre-5G elements) specified approximately 15,000 tests in the full conformance suite. 3GPP Release 15 (early 5G) specifies approximately 300,000 tests – a 20-fold increase in test complexity. We should expect that 3GPP Release 16 (pure 5G) will specify additional tests. It is worth noting that these numbers do not include coexistence testing intended to show that 5G devices and equipment will not interfere with non-5G devices in shared spectrum. As the number of tests increases, the cost of test goes up – and the need for higher test speed and test flexibility will increase.

Testing the RF Front Ends (RFFEs) of 5G equipment and devices is challenging, as the air interface frequencies range from 450 MHz to 6 GHz (in the FR1 bands) and 24.25 GHz to 52.6 GHz (in the FR2 bands) and include both licensed and unlicensed bands. Power consumption of the 5G RFFE (especially in user devices) will be a consideration, as power amplifier efficiencies tend to fall as output frequencies rise. Additionally, power management architectures on both the 5G receiver and transmitter will need to be very responsive to variations in signal level, which can change rapidly when the 5G link is using higher frequencies that are heavily influenced by line-of-sight impairments.

In 5G use profiles where high throughput is needed, the 5G baseband integrated circuit and system-on-chip devices will use extremely fast data rates – on the order of 32 gigabits per second for some SERDES interfaces in 5G NR base station equipment. Nyquist-Shannon sampling theorem requires clock rates at least twice the data rate, which implies that sampling clocks in test systems will run at speeds equal to or greater than the higher 5G air interface frequencies – this has significant implications for the design of signal integrity test fixtures and circuits. Likewise, latency requirements for 5G are at or below 1 millisecond end-to-end, which implies that test fixtures and circuits must be able to measure and manage transitions at high speed.

Given the above, it becomes obvious that digital circuits in 5G NR equipment and devices (and the testers used to analyze them) must be designed with RF techniques, with attention paid to transmission line effects, terminating impedances, and reflection of signals from mismatched terminations. In some cases, frequencies will be so high that only radiated tests will be possible, as transmission line effects and RF calibration requirements will make conducted tests impossible. For integrated circuit and system-on-chip devices at low-nanometer geometries, it will be important to analyze cross-coupling between on-chip circuit blocks.

At Elevate, we know ATE. Our high density pin electronics combine speed, flexibility and the best economic value per channel in the market. We are the choice for the largest test companies in the market, the world’s largest processor companies, and the up and coming firms bringing new, innovative chips to market. CLICK HERE to Read More About 5G Test Considerations.

MT MYSTERY UPDATE

Automatic Test Equipment Market (ATE) Today

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Typical integrated circuit (IC) solutions for pin electronics (PE) have been provided by multiple semiconductor companies in multiple different process technologies. Over the years, a typical chipset in support of all the functionality for a single device-under-test (DUT) has included bipolar, complementary bipolar, BiCMOS, SiGe BICMOS, CMOS, HV CMOS, and GaAs, as well as field programmable gate arrays (FPGAs). Each of these different technologies used for a different ATE function is packaged separately. This has led to solutions for ATE that take up a significant amount of board space, as well as a significant amount of power dissipation and cost, and the difficulties of dealing with the associated heat removal for the thermal design of a channel. This has produced limitations in the board size of a channel and limited the number of devices that can be tested in parallel, which impacts the $ / device test time. This has also been a cost and power problem. New advanced CMOS technologies provides a paradigm shift in ATE. CMOS can provide high levels of integration, large numbers of channels on a single die, and lower power and cost. The ability to integrate in CMOS will also enable the ability to test multiple devices in parallel, thus reducing test time and test cost per DUT. This trend has been initiated by new unique process features for CMOS which enables this new type of ATE. Smaller channel size, lower cost and power, and multiple DUTs tested in parallel are concepts that previously without taking advantage of the CMOS process technology evolution. Today you can fit 64 high speed digital channels on PXI instrument card and 192+ channels on a typical instrument card. This level of channel density enables testing of as many as 32, 64 or hundreds of DUT’s in parallel.

Silicon bipolar technology has been used historically for ATE pin electronics integrated circuits. This was the result of the fact that large voltage swings for the pins are needed, and the breakdown voltage of the bipolar transistor in older bipolar technologies could support these requirements. In recent years, silicon germanium (SiGe) BiCMOS technologies has also been considered for PE. There are multiple bipolar device types in SiGe technologies which allow the trade-off between breakdown voltage and device FT. Additionally, the emitter feature sizes for the SiGe bipolar device allow for more than one PE channel to be integrated onto the same die as well as some CMOS support circuitry for the controls for the pin electronics. This is the result of being able to take advantage of CMOS devices in SiGe BiCMOS technologies with channels lengths of 0.35 mm down to 0.18 mm.


Mystery: SOC Octal 500 MHz Integrated Pin Electronics

Currently, bipolar is still a consideration for pin electronics in support of board level products, for markets such as automotive, but for testing of current and future SOCs, for a number of new and emerging high volume markets, using advanced ATE, where the cost per channel ($ / channel) has become an issue for these new test platforms, CMOS has become a competitor for bipolar for a number of reasons. The current and future drive for ATE electronics is to reduce the $ / channel, as well as the physical board size per channel in the ATE, and this is a difficult proposition with either bipolar or SiGe BiCMOS. Analog mixed signal CMOS technology nodes continue to be driven downwards, along with associated breakdown voltages, but the addition of some specialty devices to these technologies, such as variable drain devices, which enable analog mixed signal CMOS devices with high breakdown voltages (HV), allow the possibility of the inclusion of pin electronics in analog mixed signal CMOS. Current HV devices support > 30V breakdown, and this will evolve to > 50V. Current PE CMOS solutions are migrating from 180 nm to 65 nm, and the HV device capability is increasing with this technology node reduction.   

The ATE support electronics are becoming SOCs themselves, with the integration of many functions that used to be separate packaged devices in specialty processes, such as timing generation, are now being able to be included in CMOS processes with high levels of integration. The ability to integrate analog and digital ATE functions into a single SOC provides the opportunity to reduce the size and cost of the ATE. Additionally, all of the signal processing and digital calibration can be included on-chip which will make the devices easier to deploy. ATE customers that currently have timing generators (TG) implemented in FPGAs now have the opportunity to include this functionality in a custom SOC that includes the PE. This integration opportunity provides the ability to have customer-specific TG IP on the same SOC as the PE. The TG will be higher resolution, lower jitter, and have more programmability and flexibility for the customer than the current FPGA solutions. Taking advantage of CMOS node scaling, this also leads to lower $ / channel, lower power, and a smaller footprint on the board.      

This push towards the reduction of board size for ATEs is also enabled by the consideration of utilizing the HV CMOS devices to replace functions that have been classically discrete devices on the boards. These CMOS HV devices also have multiple gates, which can be taken advantage of through known design techniques to support large voltage swings. The HV device also enables the integration of ATE functions such as the parametric measurement unit (PMU) and the device power supply (DPS) on the same SOC as the PE and the TG and support many channels on a single die. Thus, analog mixed signal CMOS technology is driving towards reduction of channel size and cost through the integration of multiple device types that have historically been discrete surface mount (SMT) devices and separate packaged devices in different process technologies. As the frequency performance of the HV CMOS devices continue to increase, there will be more opportunities for CMOS to rival and replace bipolar and SiGe technologies for functions in the ATE that have been historically bipolar. Currently HV CMOS can support > 200-400 MBps pin electronics. This will evolve to 2-4 GBps with analog mixed signal CMOS process evolution, with the numbers of PE channels exceeding 8. Board size per channel is a critical consideration. All functions that can be integrated through the leverage of the HV CMOS and the smaller geometry CMOS devices can take advantage of this technology to do. This will ideally result in a board with large valued capacitors and CMOS SOCs, and this shrinks the board size to the ultimate physical limits possible.   

In terms of improving channel density, analog mixed signal CMOS has provided an increase in channel density from 2 channels per chip to most commonly 8 channels per chip with the per channel power dissipation dropping by 2X to 4X lower than comparable bipolar products. The reduction in CMOS technology nodes will enable smaller packaging, lower power dissipation, higher levels of integration, and lower cost. All of these factors will contribute to a reduction in the $ / channel that CMOS will provide that bipolar will not be able to compete with. Additionally, current CMOS designs can be ported to lower nodes at a reduction in development costs as well as production cost. The utilization of advanced analog mixed signal CMOS can be used to develop SOC solutions for ATE customers that will provide a reduction in $ / channel cost for the final ATE product. The future of ATE is testing SOCs with higher pin counts and higher speeds, as the CMOS technology nodes continue to shrink. In order to meet these challenges, ATE chip solutions are needed that keep pace. It is an obvious natural progression for the PE and supporting ATE functions to shrink as well to keep up. There is the opportunity to realize this trend and continue down this path to provide unique ATE solutions that provide high speed ATE solutions at lower power, while reducing $ / channel and accompanying board space. Unique ATE SOC solutions can provided based on this realization to your company and allow you to provide a solution that is a discriminator in the ATE marketplace.    

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