The Digital Design Engineer is responsible for designing digital circuits used in ATE ASICs or verifying digital circuits, depending on project needs.  Will work with the project lead to define the functional requirements.  Will work with the analog team to help integrate the digital circuit into the device.  Verification entails working with the design team to understand the device functionality and creating a SystemVerilog or UVM testbench and tests to verify those functions.  May be required to define timing constraints and work with the physical implementation team to ensure a correct final result. 

Responsibilities

• Understand the design requirements and help with defining the final circuit 
• Design the digital circuit using SystemVerilog 
• Testbench and test creation for verifying the digital circuit 
• Work with the ASIC team to help integrate digital function into the device 
• Define timing constraints for the design 
• Work with physical implementation team to meet timing and area constraints 

Requirements

• BS in Electrical Engineering is required 
• 3+ years of experience in digital semiconductor circuits 
• Experience with Cadence tool flow 
• Understanding of verification methodology 
• SystemVerilog proficiency 
• Strong verbal and written communication skills 

Preferences

• UVM is a plus 
• Experience with scripting languages is a plus 
• Experience with benchtop or ATE testing is a plus