Month: August 2020

ATE digital systems traditionally consist of sequencers, formatters, timing generators and pin electronics. The decision about which components to use for each section of the design is primarily driven by performance specifications and cost desired. These components range from discrete, fully custom ASIC, Field Programmable Gate Array or commercially available parts.

Field Programmable Gate Arrays (FPGA) provide flexibility and have been used for the sequencer and timing/formatting for low to medium performance ATE digital subsystems.

Implementing the sequencer with an FPGA provides flexibility to customize the digital subsystem for logic, memory or mixed signal test. The FPGA clocking required is typically well within the specifications of the target FPGA. The sequencer and pattern execution stages are typically what make each system unique compared to the competitors offering.

The format and timing functionality are typically similar amongst different ATE platforms. The differences are in the cycle to cycle edge placement resolution and accuracy as well as the fine skew control used for channel deskew calibration. The fine deskew control is often available in the pin electronics ICs.

FPGAs have been successfully used for the timing and format function, but the FPGA quickly becomes the limiting factor as the system performance requirements increase to above 50-100Mhz pattern rates and as the system edge placement accuracy is pushed below 1ns. While the SERDES engines in the FPGA I/O structures can provide <100ps resolution, implementing this reliability for edge to edge timing placement increases the design time and pushes the designer to choose larger and more expensive FPGA.

The most common usage of the SERDES blocks are for various communications protocols such as PCIe and the FPGA design tools provide excellent tools for designing and characterizing these functions. Designers often run into roadblocks when designing the timing section using these SERDES blocks and there are limited tools available from FPGA vendors to resolve issues. Designers often spend 10X the budgeted engineering hours implementing and characterizing these timing circuits. Typical issues include: inconsistent linearity from channel to channel, higher than acceptable jitter, and difficulty routing the design from run to run.

As designers attempt to increase the channel count they are required to migrate to larger and more expensive FPGAs. In the past, designers have been able to capitalize on faster and larger FPGAs at lower costs. In recent times, however, the focus of FPGA companies has been to increase compute capabilities to address the data center and artificial intelligence markets. This addition of more compute elements has increased the costs with minimal or negative benefits to the ATE designer. In addition, the costs of older devices that serve the ATE market have started going up dramatically especially for larger devices. This has pushed the cost for higher channel ATE using larger FPGAs up to $50/channel just for the FPGA.

To achieve higher performance ATE with pattern rates of 200+ MHz, ATE designers need to use custom or commercially available format and timing generator ICs. They are then able to use a reasonable cost FPGA for the sequencer portion of the design.

A commercially available timing generator would provide smaller ATE companies to migrate up the performance ladder in digital ATE instrumentation. These chips are designed to be interfaced to high performance pin drivers without requiring an over constrained FPGA I/O.

By purchasing timing chips with high end performance this would reduce the design, characterization and test times as well as reducing the cost per channel while offering higher performance digital ATE specifications. The timing accuracy is specified by the vendor and does not require extensive characterization and production testing of these parameters at system test.

Commercial timing chips will ultimately save an ATE company development cost and time to market as well as overall cost of the system, while providing a path to higher end performance.

The mobile industry processor interface (MIPI®) standard defines industry specifications for the design of mobile devices such as smartphones, tablets, laptops and hybrid devices. MIPI interfaces play a strategic role in 5G mobile devices, connected car and Internet of Things (IoT) solutions. The MIPI standard defines three unique physical (PHY) layer specifications: MIPI D-PHY®, M-PHY® and C-PHY®. MIPI D-PHY and C-PHY physical layers support camera and display applications, while the high-performance camera, memory and chip-to-chip applications are supported on top of the M-PHY layer.

MIPI is managed by MIPI Alliance which is a collaboration of mobile industry leaders which include Intel, Nokia, Samsung, Motorola, TI, ST etc.  The objective of MIPI Alliance is to promote open standards for interfaces to mobile application processors. This will help in having new services to mobile users at faster rate.

In the mobile market, MIPI Alliance specifications are targeted to mobile devices that operate on mobile networks. Typical devices are smartphones, tablets, laptops and hybrid devices. MIPI Alliance provides specifications that serve manufacturers’ various needs for physical layer, multimedia, chip-to-chip or interprocessor communications (IPC), control/data, debug/trace, and software integration applications.

All of the specifications are designed to address three characteristics essential to successful mobile designs:  1) low power to preserve battery life; 2) high-bandwidth to enable feature-rich, data-intensive applications, and 3) low electromagnetic interference (EMI) to minimize interference between radios and other subsystems in a device.

Smartphones

The smartphone industry is the largest single market for MIPI specifications. All major chip vendors use MIPI Alliance specifications and all smartphones on the market include at least one MIPI specification. MIPI specifications are used in hundreds of millions of smartphones.

MIPI Alliance specifications cover the full range of interface needs in a device. The specifications can be applied to integrate the modem, application processor, camera, display, audio, storage, antennas, tuner, power amplifier, filter, switch, battery, sensors, and other components.

Component vendors and device manufacturers use MIPI Alliance specifications because the technologies simplify designs, reduce design costs and shorten time-to-market for efficient, high-performing products. And fundamentally, each specification is optimized to ensure three performance characteristics needed in a mobile device: low power to preserve battery life, high-bandwidth to enable feature-rich applications, and low electromagnetic interference (EMI) to optimize performance of radios and subsystems.

Tablets, laptops and hybrid devices

Devices that converge mobile and computing capabilities are important markets for MIPI Alliance specifications. MIPI specifications helped establish and advance the tablet market and many organizations in the PC industry use MIPI specifications in mobile-connected laptops, tablet/laptop hybrids and other devices. Typical use cases for MIPI specifications in these devices include connecting and managing power consumption for high-definition displays and minimizing the number of wires deployed through hinges to connect cameras or displays.

 Specifications

MIPI specifications address only the interface technology, such as signaling characteristics and protocols; they do not standardize entire application processors or peripherals. Products which utilize MIPI specs will retain many differentiating features. By enabling products which share common MIPI interfaces, system integration is likely to be less burdensome than in the past.[8]

MIPI is agnostic to air interface or wireless telecommunication standards. Because MIPI specifications address only the interface requirements of application processor and peripherals, MIPI compliant products are applicable to all network technologies, including GSM, CDMA2000, WCDMA, PHS, TD-SCDMA, and others.

Some of the specifications by MIPI include:

• Camera Serial InterfaceDisplay Serial Interface
• Display pixel interface
• System Power Management Interface (SPMI)
• SoundWire, introduced in 2014[12]

MIPI CSI Interface

CSI stands for Camera Serial Interface. It specifies high speed serial interface between a host processor and camera module. Figure-2 depicts MIPI CSI-2 Interface.

Following are the features of MIPI CSI-2 Interface.

• It is high performance serial interface between image sensor and application processor.
• It uses D-PHY physical layer with upto 4 data lines which provides data throughput of about 4Gbps.
• Separate I2C compliant interface used for camera control functions as shown.
• MIPI CSI interface offers following benefits.
• Scalability • Lower power • improved reliability • lower system cost

MIPI DSI Interface

 DSI stands for Display Serial Interface. It is High speed and high performance serial interface. The DSI interface offers efficient, low power and low pin count connectivity between application processor and display module (or display bridge IC). It uses MIPI D-PHY as physical layer. Following are the features of MIPI D-PHY.

• It uses 4 data lines with 1 common differential line
• Throughput upto 1Gbps can be achieved.
• Both pixel and data commands are serialized into single physical stream between processor and display IC. The status is conveyed from display IC to application processor.

MIPI Testing

MIPI DESIGN AND SIMULATION

You need to design mobile devices that address the evolving data storage, data transfer, display, camera, memory, power, and other requirements defined by MIPI specifications. Customers demand higher performance, real time streaming of multimedia content and feature-rich applications.

MIPI TRANSMITTER TEST

You need to test the performance of your MIPI transmitter device to ensure it is not the root cause of signal impurities at the receiving end of the transmission line. MIPI D-PHY, M-PHY and C-PHY all have unique transmitter test challenges. With hundreds of tests to be performed, you can save significant test time by using automated compliance test software.

MIPI RECEIVER TEST

You need to test your MIPI receiver device to ensure it can properly detect the digital signal content of an input signal. It is important to test it against a worst-case stress condition to account for signal degradation in the transmission channel. You need an accurate high-speed signal stimulus, as well as bit error detection capabilities, to test the performance of your MIPI receiver. Automated compliance test software enables you to quickly test all key parameters of your designs.

MIPI PROTOCOL TEST

Protocol validation occurs predominately at the interface layer. There are many different protocols supported on the PHY layer of the MIPI specifications, including CSI-2, DSI-1, DigRF, CSI-3, UFS, UniPro, SSIC, and MPCIe. Each protocol has its own unique requirements and tests. For both MIPI D-PHY and M-PHY protocols, there is a stack between the physical and link layer, as well as between the transport and high-level application layer. To truly identify where an error exists, it is ideal to be able to “see into” that stack.

How MIPI Interfaces Enable 5G Smartphones

The first wave (phase 1) of high-end 5G smartphones is expected to be an enhancement of the high-end 4G devices currently on the market. Major enhancements will include the addition of the new 5G NR RF subsystem, and the evolution of other subsystems to enable better user experiences and richer multimedia capabilities. For example, these 5G smartphones may have three to four high-resolution rear cameras with high-frame-rate/slow-motion video capture capability, an enhanced microphone array, multi-channel audio and stereo speakers.

The 5G modem and application processor use MIPI specifications such as CSI-2 for cameras and DSI-2 for the display, as well as either the low-power, high-bandwidth, pin-efficient MIPI D-PHY or C-PHY physical layers. MIPI RFFE for RF front-end devices control, and MIPI UniPro with M-PHY for high-performance flash storage are all becoming ubiquitous in 5G designs. MIPI I3C, SoundWire, SLIMbus and upcoming VGI specifications are expected to be adopted in many upcoming 5G smartphone platforms as well.

MIPI CSI-2

MIPI CSI-2 is the most widely used camera interface in mobile and other markets. It has achieved widespread adoption for its ease of use and ability to support a broad range of high-performance applications, including 1080p, 4K, 8K and beyond video, and high-resolution photography.

Designers should feel comfortable using MIPI CSI-2 for any single- or multi-camera implementation in mobile devices. The interface can also be used to interconnect cameras in head-mounted virtual reality devices; automotive smart-car applications for infotainment, safety, or gesture-based controls; imaging applications for client content creation and consumption products; camera drones; IoT appliances; wearables; and 3D facial recognition security or surveillance systems.

The latest release, MIPI CSI-2 v3.0, delivers enhancements to the specification designed to enable greater capabilities for machine awareness across multiple application spaces, such as mobile, client, automotive, industrial IoT and medical. RAW-24, for representing individual image pixels with 24-bit precision, is intended to enable machines to make decisions from superior quality images; an autonomous vehicle, for example, could decipher whether darkness on an image is a harmless shadow or a pothole in the roadway to be avoided. Smart Region of Interest (SROI)—for analyzing images, inferencing algorithms and making better deductions—could enable machines on a factory floor, for example, to more quickly identify potential defects on a conveyor belt, or medical devices to more surely recognize anomalies such as tumors. And Unified Serial Link (USL)—for encapsulating connections between an image sensor module and application processor—is crucial for reducing the number of wires needed in IoT, automotive and client products for productivity and content creation, such as all-in-one and notebook platforms.

MIPI CSI-2 can be implemented on either of two physical layers from MIPI Alliance: MIPI C-PHY v2.0 or MIPI D-PHY v2.5. It is backward compatible with all previous MIPI CSI-2 specifications. Performance is lane-scalable, delivering, for example, up to 41.1 Gbps using a three-lane (nine-wire) MIPI C-PHY v2.0 interface, or 18 Gbps using four-lane (ten-wire) MIPI D-PHY v2.5 interface under MIPI CSI-2 v2.1.

Testing of MIPI-Specification-Based Devices

The latest trend for semiconductor device manufacturers is to add several high-speed MIPI® specification-based ports to a single device. This enables feature-rich implementations of imaging- and display-intensive applications, although it also poses significant challenges for production test engineers who are tasked with creating high-fault coverage testing solutions on automated test equipment (ATE). Such fault coverage often entails creating a parallel, at-speed, system-oriented functional test while simultaneously grappling with the limitations of legacy ATE and the complexity of the MIPI protocols being tested.

There are three high speed PHY-layer standards defined by MIPI, and they are used for different applications:

• D-PHY is a variable speed unidirectional clock synchronous streaming interface, with low speed in-band reverse channel and supports interfaces for camera (CSI), and display (DSI).
• M-PHY is performance driven, bidirectional packet/network oriented interface supporting interfaces like camera (CSI), storage (UFS), DigRF, and the UniPro, LLI, SSIC, M-PCIe which are used for inter-processor communications
• C-PHY is a variable speed unidirectional, embedded clock streaming interface, with low speed in-band reverse channel and supports interfaces for camera (CSI), and display (DSI).

Each interface provides a wide range of parameters including clocking method, channel compensation, number of pins, maximum amplitude, data rate and format, bandwidth per port, data encoding, and clock recovery. The D-PHY, M-PHY, and C-PHY MIPI interfaces are not controlled by a compliance program because they are not accessible to users. However, validation of specification conformance is important to semiconductor vendors and system integrators to ensure interoperability between components.

The MIPI specifications and Conformance Test Suite (CTS) requirements for components are quite complex and testing them is challenging. Connectivity to the Device Under Test (DUT) while making sure signal integrity is maintained, creating the worst-case stimulus for the DUT while not overstressing it, or getting test result information from the DUT are examples of such challenges.

BER test solutions offer the flexibility to test all types of MIPI receivers accurately by providing accurate high speed signal stimulus and bit error detection capabilities. More complex C-PHY and D-PHY signal stimulation can be addressed with high performance arbitrary waveform generators. Automated test software helps to reduce test development and execution time while ensuring repeatability and accuracy.

Elevate competitive advantage in ATE

Elevate is a leading supplier of innovative, low power, high density components for the design of next generation Automated Test Equipment (ATE). With a proven track record of consistently delivering the highest density, lowest power solutions available, systems designed around Elevate products have a competitive advantage in the ATE market space and are able to adapt successfully to emerging trends and challenges while providing ever increasing end user value.

Elevate offers a wide variety of solutions for the ATE market with variable levels of integration so that we can serve the unique requirements of multiple end user segments such as System on a Chip (SOC) Test, Memory Test, Test During Burn-in (TDBI), In-Circuit Test (ICT) and beyond.

Elevate’s mission is to serve our semiconductor and system test customers by providing world class test integrated circuits (ICs) that address the industry’s most complex ATE challenges.  We strive to exceed our customer’s expectations, now and well into the future, through designing the lowest power/highest density solutions, with the goal of providing the lowest possible cost of test.